module r02cx_a_ctrl
			(
/*
================================================================================
Beggining of user changeable code
Part 1. IO description
*/
			 clock, resetn,
			 DATA_IN,
			 DIPSWn,
			 RESET_VIEWn, ZINn, ZOUTn,
			 LEFTn, RIGHTn, UPn, DOWNn,
			 RESET_CISn, EN_CIS,

			 gROW_SELn, gRESET_PIXELn, gTXn,
			 S1, S2, S3, S4, RESET_LOGICn,
			 RESET_ROWTKNn, ADV_ROWTKNn,
			
			 CLK_CISn,
			 ENA_CNT, WR, SET_SRAM, ADV_TKNn,
			 PCn, ENA_WL, DLn, ODD_SEL,
			 load_podreg,
			
			 RAMP_LATCH, RAMP_DB,
			 POD_CLKn, POD_DB,
			
			 VSYNC, HSYNC
			);

input			clock, resetn;
input	[9:0]	DATA_IN;
input	[7:0]	DIPSWn;
input			RESET_VIEWn, ZINn, ZOUTn;
input			LEFTn, RIGHTn, UPn, DOWNn;
input			RESET_CISn, EN_CIS;
output			gROW_SELn, gRESET_PIXELn, gTXn;
output			S1, S2, S3, S4, RESET_LOGICn;
output			RESET_ROWTKNn, ADV_ROWTKNn;

output			CLK_CISn;
output			ENA_CNT, WR, SET_SRAM, ADV_TKNn;
output			PCn, ENA_WL, DLn, ODD_SEL;
output			load_podreg;

output			RAMP_LATCH;
output	[13:0]	RAMP_DB;

output			POD_CLKn;
output	[13:0]	POD_DB;
output			VSYNC, HSYNC;

/*
End of user changeable code
Part 1.
================================================================================
*/

/*
================================================================================
Beggining of user changeable code
Part 2. Definition of microprocessor generated internal control signal
*/

wire			load_podreg;
wire			sclr_rampcnt, cnten_rampcnt;
wire			pHSYNC;

/*
End of user changeable code
Part 2.
================================================================================
*/

/* Definition of wires for interfacing processor core */
wire	[11:0]	INITA;
wire	[15:0]	INITB;

wire	[3:0]	PERIINIT;
wire	[3:0]	PERIADDRREG;
wire	[7:0]	PERICTRLREG;
wire	[15:0]	PERIVALREG;

wire	[7:0]	INTFLAG;

wire	[11:0]	PORTA;
wire	[15:0]	PORTB;

wire	[7:0]	rDIPSW;

wire	[27:0]	rA, rB;			// For direct accessing registers in microprocessor

proccore	proccore_inst (.clock(clock), .resetn(resetn),
						   .rDIPSW(rDIPSW),
						   .INITA(INITA), .INITB(INITB),
			 			   .PORTA(PORTA), .PORTB(PORTB),
			 			   .rA(rA), .rB(rB),

			 			   .INTFLAG(INTFLAG),
			 			   .PERIINIT(PERIINIT), .PERIADDRREG(PERIADDRREG),
			 			   .PERICTRLREG(PERICTRLREG), .PERIVALREG(PERIVALREG));

dipswreg	DIPSWREG1	(.clock(clock), .resetn(resetn), .DATAn(DIPSWn), .Q(rDIPSW));

/*
================================================================================
Beggining of user changeable code
Part 3. Assignment of PORTA[11:0] and PORTB[15:0]
*/

assign		gRESET_PIXELn	= PORTA[11];
assign		gTXn			= PORTA[10];
assign		RESET_ROWTKNn	= PORTA[9];
assign		ADV_ROWTKNn		= PORTA[8];
assign		S1				= PORTA[7];
assign		S2				= PORTA[6];
assign		S3				= PORTA[5];
assign		RESET_LOGICn	= PORTA[4];
assign		VSYNC			= PORTA[3];
assign		pHSYNC			= PORTA[2];
assign		gROW_SELn		= PORTA[1];
assign		S4				= PORTA[0];

assign		load_podreg     = PORTB[14];
assign		cnten_rampcnt   = PORTB[13];
assign		sclr_rampcnt    = PORTB[12];

assign		ODD_SEL         = PORTB[10];
assign		DLn             = PORTB[9];
assign		ENA_WL          = PORTB[8];
assign		PCn             = PORTB[7];
assign		ADV_TKNn        = PORTB[6];
assign		WR              = PORTB[5];
assign		RAMP_LATCH      = PORTB[4];
assign		ENA_CNT         = PORTB[3];
assign		SET_SRAM		= 0;

assign		CLK_CISn        = PORTB[0];

assign		INITA			= 12'b1111_0001_0000;		// Initial value of PORTA
assign		INITB			= 16'b0000_0110_1100_0111;	// Initial value of PORTB

/*
End of user changeable code
Part 3.
================================================================================
*/

wire			STARTn;									// STARTn should be connected to
														// GND or VCC if it does not used

wire			init_adc0, init_adc1, init_dac0;		// Initiating signal for serial ADCs
wire			idle_adc0, idle_adc1, idle_dac0;		// Idle signal of serial ADCs
														// idle_* should be connected to
														// GND or VCC if they do not used

assign			init_adc0 = PERIINIT[0];
assign			init_adc1 = PERIINIT[1];
assign			init_dac0 = PERIINIT[2];

assign			INTFLAG = {4'b0000, idle_dac0, idle_adc1, idle_adc0, ~STARTn};

/*
================================================================================
Beggining of user changeable code
Part 4. Instantiation of peripheral logics
*/

wire	[3:0]	gain;
wire	[13:0]	offset;

vclkgen		VCLKGEN1	(.clock(clock), .resetn(resetn),
						 .pHSYNC(pHSYNC), .dtCLK(load_podreg),
						 .dHSYNC(HSYNC), .vCLK(POD_CLKn));

rampvargen	RAMPVARGEN1	(.SEL(rDIPSW[1:0]), .gain(gain), .offset(offset));

crampcnt	CRAMPCNT1	(.clock(clock), .resetn(resetn),
						 .sclr(sclr_rampcnt), .cnten(cnten_rampcnt),
						 .gain(gain), .offset(offset), .satlevel(10'h000),
						 .Q(RAMP_DB));

/* Note
Signals which consist INTFLAG should be connected to GND or VCC if they are not used.
These signals include idle_dac0, idle_adc0, idle_adc1 and STARTn.
*/

assign		idle_dac0 = 0;
assign		idle_adc1 = 0;
assign		idle_adc0 = 0;
assign		STARTn = 0;

/*
End of user changeable code
Part 4.
================================================================================
*/

/*
================================================================================
Beginning of user changeable code
Part 5. Output mux definition
*/

/*
End of user changeable code
Part 5.
================================================================================
*/

wire	[15:0]	DATA_DB;

/*
================================================================================
Beginning of user changeable code
Part 6. Assignment of logic analyzer pod data
*/


wire			dbroll;

lpm_datacomp lpm_datacomp_inst (.dataa(DATA_IN), .datab(10'h0FF), .ageb(dbroll));
assign			DATA_DB = {8'b0, (rDIPSW[2])? DATA_IN[9:2] : ((dbroll)? 8'hFF : DATA_IN[7:0])};

/*
End of user changeable code
Part 6.
================================================================================
*/
wire	[15:0]	Q_POD;
podreg			PODREG1	(.clock(clock), .resetn(resetn), .load(load_podreg),
						 .DATA(DATA_DB),
						 .Q(Q_POD));
assign			POD_DB[13:0] = Q_POD[13:0];
endmodule